A Schottky diode is a unipolar device using electrons as carriers. Since the carrier recombination is nearly eliminated, the switching speed is high. Moreover, in response to a low forward bias voltage, the Schottky diode has higher forward current and shorter reverse recovery time. In response to a high reverse bias voltage, the Schottky diode has the relatively high reverse leakage current. The high reverse leakage current is related to the Schottky barrier determined by the metal work function of the metal electrode, the band gap of the intrinsic semiconductor, the type and concentration of dopants in the semiconductor layer, and other factors. In contrast to the Schottky diode, a P-N junction diode is a bipolar device that can pass more current than the Schottky diode. However, the P-N junction diode has a forward turn-on voltage higher than that of the Schottky diode, and takes longer reverse recovery time due to a slow and random recombination of electrons and holes during the recovery period.
For combining the benefits of the Schottky diode and the P-N junction diode, a configuration of a gated diode has been disclosed. The gated diode has comparable or lower forward turn-on voltage with respect to the Schottky diode. The reverse leakage current of the gated diode is similar to the P-N junction diode, but is lower than the Schottky diode. The reverse recovery time at high temperature of the gated diode is close to or slightly longer than the Schottky diode. The interface tolerance temperature of the gated diode is higher than the Schottky diode. In practical applications, the gated diode is advantageous over the Schottky diode.
A typical gated diode has been disclosed in U.S. Pat. No. 6,624,030, which is entitled “Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region”. Please refer to FIGS. 1A˜1L, which schematically illustrate a method of manufacturing a gated diode.
Firstly, as shown in FIG. 1A, an N+ substrate 20 with an N-epitaxial layer 22 grown thereon is provided, wherein a field oxide layer 50 is grown on the surface of the N− epitaxial layer 22. Then, as shown in FIG. 1B, a photoresist layer 52 is formed on the field oxide layer 50. A first photolithography and etching process is performed to partially remove the field oxide layer 50. Then, a first ion implantation process is performed to dope the substrate with boron ion (B+) through openings in the photoresist layer 52. After the photoresist layer 52 is removed, a boron thermal drive-in process is perform to form edge P-doped structures 28 and a center P-doped structure 30 (see FIG. 10). Then, a second ion implantation process is performed to dope the substrate with BF2. Then, a second photolithography and etching process is performed to use a photoresist layer 54 to cover the periphery of the device area and remove the field oxide layer 50 in the center of the device area (see FIG. 1D and FIG. 1E).
After the photoresist layer 54 is removed, a gate oxide layer 56, a polysilicon layer 58 and a silicon nitride layer 60 are sequentially grown, and an arsenic implantation process is made (see FIG. 1F). Then, as shown in FIG. 1G, an oxide layer 62 is formed on the resulting structure of FIG. 1F by a chemical vapor deposition (CVD) process. Then, a third photolithography process is performed to form a gate-pattern photoresist layer 64 over the oxide layer 62. Then, a wet etching process is performed to etch the oxide layer 62 while leaving the oxide layer 62 under the gate-pattern photoresist layer 64 (see FIG. 1H). Then, as shown in FIG. 1I, a dry etching process is performed to partially remove the silicon nitride layer 60, and a third ion implantation process is performed to dope the substrate with boron ion (B+). Consequently, a P-type layer 66 of a channel region is formed.
Then, as shown in FIG. 1J, the remaining photoresist layer 64 is removed, and a fourth ion implantation process is performed to dope the substrate with boron ion (B+) to form a laterally-graded P-type pocket 36. Then, a wet etching process is performed to remove the silicon oxide layer 62, and a dry etching process is performed to partially remove the polysilicon layer 58 (FIG. 1K). Then, as shown in FIG. 1L, a wet etching process is performed to remove the remaining silicon nitride layer 60, and an arsenic implantation process is performed to form an N-doped source/drain region 24. Meanwhile, some fabricating steps of the gated diode have been done. After subsequent steps (e.g. metallic layer formation, photolithography and etching process, and so on) are carried out, the front-end process of the wafer is completed.
In comparison with the Schottky diode, the gated diode fabricated by the above method has comparable forward turn-on voltage, lower reverse leakage current, higher interface tolerance temperature, better reliability result. However, since the gated diode has longer reverse recovery time (at the room temperature) than the Schottky diode, the device performance is deteriorated.